A Course chapter on Quantum Computing for Master Students in Engineering

Quantum computing is a rapidly evolving field encompassing various disciplines such as physics, mathematics, computer engineering, and computer science. Teaching quantum computing in a concise and effective manner can be challenging, especially within the time constraints of a single course or a short period, even for graduate students. This challenge is particularly relevant in two-year MSc programs that include a thesis, which is a typical structure in higher education systems in the USA and Europe. In this paper, the author proposes an approach to teaching quantum computing and shares their experience of conducting a course chapter on the subject within a two-week time frame. The experience reported in this paper is integrated into the "Technologies of Computing Systems" (TCS) course, with a total workload of 6 ECTS (in the context of the European Credit Transfer and Accumulation System, one ECTS corresponds to 28 hours of work), conducted in one quarter, over seven weeks. The structure of the course chapter is discussed, involving a series of lectures that were accompanied by lab classes and a lab project, allowing students to receive guidance while also engaging in hands-on learning and independent study. The paper provides an overview of the quantum computing topics covered, and their integration in the TSC course, and gives details about how these topics are studied in the different types of classes. It also discusses the evaluation procedure and presents the results obtained. It can be concluded that the inclusion of the quantum computing component not only significantly increased student interest in the course but also effectively bridged the gap between classical and quantum computing for engineering students within a short period of two weeks.Comment: 10 pages, 7 figure

Applying matrix decomposition techniques to edge detection operators

In this paper decomposition techniques are applied to derivative operators, used for image edge detection. It is shown that the application of decomposition techniques to common edge detectors can result in substantial savings in computing time. For a 25x25 Laplacian of Gaussian, mask, an improvement of six times less arithmetic operations is achieved when decomposition techniques are applied.We also show that these techniques are advantageous for hardware realization of the filters. The memory required to a 2-D (nxn)-th order FIR filter direct realization with distributed arithmetic is O(2(n+1) ) while the worst case for the decomposed filter is O(n x 2n)

Codificador de vídeo baseado na transformada de ôndulas 3D

Neste artigo apresenta-se um codificador de vídeo baseado na transformada de ôndulas, com interface do tipo Windows®, desenvolvido em Borland C++ Builder v5.0. O codificador tira partido das características da estrutura hierárquica 3D de coeficientes da DWT, resultante da sua aplicação no domínio do tempo e do espaço. O utilizador escolhe a sequência a codificar (armazenada em ficheiro), o número de tramas, o nível de decisão, e a ôndula a considerar na DWT no espaço, podendo obter resultados do desempenho do codificador, e guardar esses valores em ficheiros compatíveis com Microsoft® Excel. Pode, também, visualizar alguns resultados intermédios do processo de codificação, nomeadamente a decomposição por aplicação da DWT no tempo e no espaço, conferindo a este trabalho, também, um cariz didáctico

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps)

Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems

This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The considered methodology adopts a simple and efficient core interconnection mechanism to easily allow the inclusion and the removal of such optimized processing cores. Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology. For the considered system, speedup factors greater than 15 were obtained with a very modest increase of the involved hardware resources.info:eu-repo/semantics/publishedVersio

Aplicação de apoio para a aeronave P-3C CUP+ ORION : Weight & Balance : desenvolvimento de uma aplicação de apoio à distribuição do peso na aeronave que equipa a Esquadra 601 da Força Aérea Portuguesa

Simpósio realizado no Porto de 4-5 de setembro de 201

Efficient Parallel Video Encoding on Heterogeneous Systems

Proceedings of: First International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2014). Porto (Portugal), August 27-28, 2014.In this study we propose an efficient method for collaborative H.264/AVC inter-loop encoding in heterogeneous CPU+GPU systems. This method relies on specifically developed extensive library of highly optimized parallel algorithms for both CPU and GPU architectures, and all inter-loop modules. In order to minimize the overall encoding time, this method integrates adaptive load balancing for the most computationally intensive, inter-prediction modules, which is based on dynamically built functional performance models of heterogenous devices and inter-loop modules. The proposed method also introduces efficient communication-aware techniques, which maximize data reusing, and decrease the overhead of expensive data transfers in collaborative video encoding. The experimental results show that the proposed method is able of achieving real-time video encoding for very demanding video coding parameters, i.e., full HD video format, 64×64 pixels search area and the exhaustive motion estimation.This work was supported by national funds through FCT – Fundação para a Ciência e a Tecnologia, under projects PEst-OE/EEI/LA0021/2013, PTDC/EEI-ELC/3152/2012 and PTDC/EEA-ELC/117329/2010